1. Field of the Invention
The present invention relates to a differential sense amplifier in a CMOS semiconductor integrated circuit and to a dynamic logic circuit applying the same.
Here, a "dynamic logic circuit" means a logic circuit of a type which alternates between two phases, that is, an "idle phase" where it initializes the potential of internal nodes and a "working phase" where it evaluates the logic according to an input signal and defines the potential of an output node, according to a clock or other control signal.
2. Description of the Related Art
FIG. 1 is a circuit diagram of an example of the configuration of a conventional differential sense amplifier circuit (refer to Dinesh Somaseckhar and Kaushik Roy, "Differential Current Switch Logic: A Low Power DCVS Logic Family", IEEE JSSC, vol. 31, no. 7, pp. 981-991, July 1996).
This differential sense amplifier circuit 10 has, as shown in FIG. 1, p-channel MOS (PMOS) transistors PT11 to PT13, n-channel MOS (NMOS) transistors NT11 to NT15, logic Input terminals TF and TFX, logic output terminals TH and THX, a clock input terminal TCLKX, and a completion signal use output terminal TDONE indicating definition of the logic.
A source of the PMOS transistor PT11 is connected to a supply line of a power supply voltage V.sub.DD, while a drain is connected to sources of the PHOS transistors PT12 and PT13 and the completion signal use output terminal TDONE.
The drains and gates of the PMOS transistor PT12 and the NMOS transistor NT11 are connected to each other to configure an inverter INV11.
An output node ND11 of the Inverter INV11 is configured by a connection point of the PMOS transistor PT12 and the NMOS transistor NT11, while an input node ND12 of the inverter INV11 is configured by the connection point of the gates.
Similarly, the drains and the gates of the PMOS transistor PT13 and the NMOS transistor NT12 are connected to each other to configure an inverter INV12.
An output node ND13 of the inverter INV12 is configured by the connection point of the drains of the PMOS transistor PT13 and the NMOS transistor NT12, while an input node ND14 of the inverter INV12 is configured by the connection point of the gates.
The sources of the NMOS transistors NT11 and NT12 are grounded.
The output node ND11 of the inverter INV11 is connected to the input node ND14 of the inverter INV12 and the logic output terminal TH, while the output node ND13 of the inverter INV12 is connected to the input node ND12 of the inverter INV11 and the logic output terminal HX.
Further, the NHOS transistor NT15 Is connected between the input node ND12 of the inverter INV11 and the input node ND14 of the Inverter INV12, In other words, between the gate of the NMOS transistor NT11 and the gate of the NMOS transistor NT12.
Further, the NMOS transistor NT13 is connected between the logic output terminal TH and the logic input terminal TF, while the NMOS transistor NT14 is connected between the logic output terminal THX and the logic input terminal TFX.
Further, the gate of the PMOS transistor PT11 and the gate of the NMOS transistor NT15 are connected to the clock input terminal TCLKX, the gate of the NMOS transistor NT13 is connected to the input node ND12 of the inverter INV11 and the gate of the NMOS transistor NT14 Is connected to the input node ND14 of the inverter INV12.
The differential sense amplifier circuit 10 having the above configuration is a DCSL (differential current switch logic) 3 type sense amplifier circuit described in the above document.
Below, an explanation will be made of the principle of the operation of this differential sense amplifier circuit 10 in relation to FIG. 2 and FIG. 3 showing simulation waveforms.
Note that, here, a base point at which the phase switches from the idle phase to the working phase Is assumed to be the rising edge of a clock CLK. In a sense amplifier circuit of the DCSL3 type, the trailing edge of the control signal is made the base point to the working phase, therefore, in the following explanation, an inverted signal CLK_X of the clock will be introduced and used in the explanation.
FIG. 2 is a view of the operation waveform (simulation result) of a sense amplifier circuit of the DCSL3 type at the rising of the clock CLK, that is, at the falling of the clock inverted signal CLK_X. Further, in other words, FIG. 2 shows a process by which the phase switches from the idle phase to the working phase at the trailing edge of the clock CLK_X and by which the logic is therefore defined.
Further, FIG. 3 is a view of the operation waveform (simulation result) of a sense amplifier circuit of the DCSL3 type atbthe falling of the clock CLK, that is, at the rising of the clock inverted signal CLK_X.
In FIG. 2 and FIG. 3, the abscissas indicate the time, and the ordinates indicate the voltage.
As shown in FIG. 2, in the differential sense amplifier 10, when the clock inverted signal CLK_X has a logic "1" and the phase is the idle phase, the logic outputs H and H_X do not become a complete potential 0V, but rise by exactly an amount of a threshold value of the MOS.
The levels of these logic outputs H and H_X, that is, the potentials of the logic output terminals TH and THX, are also transferred to gate electrodes of the NMOS transistors NT13 and NT14, whereby both NMOS transistors NT13 and NT14 are cut off.
For this reason, a state where a not illustrated logic tree connected to the logic input terminals TF and TFX and the sense amplifier circuit 10 are electrically out off is exhibited.
Then, when the clock inverted signal CLK_X becomes a logic "0" and the phase is the working phase, the PMOS transistor PT11 becomes ON, a current flows through the PMOS transistors PT12 and PT13, and the potentials of the logic output terminals TH and THX start to rise. The potentials of the logic output terminals TH and THX at this node are also transferred to the gate electrodes of the NMOS transistors NT13 and NT14, therefore both NMOS transistors NT13 and NT14 start to become ON and start to pass current from the sense amplifier to the logic input terminals TF and TFX.
As will be explained later, there is a difference between the currents flowing to the logic input terminals TF and TFX. The sense amplifier configured by the PMOS transistors PT11 to PT13 and the NMOS transistors NT11 and NT12 increases the potential difference between the logic outputs H and H_X according to that difference to define the logic.
At this time, either of the logic outputs H and H_X becomes the logic "0" without fail. In the example Ln the figure, the logic output H_X has become the logic "0".
For this reason, the NMOS transistor NT13 having a connection relationship with respect to the logic output terminal THX becomes cut off. This NMOS transistor NT13 is a switch for controlling the connection with respect to the logic input terminal TF.
Accordingly, the current flowing into the logic input terminal TF can be suppressed to the required minimum limit.
When the clock inverted signal CLK_X becomes the logic "1" and the phase is the idle phase, the NMOS transistor NT15 becomes ON.
By this, the charge existing on an output line including the terminal TH of the logic output H flows onto the output line including the terminal THX of the logic output H_X through the NMOS transistor NT15, whereby the potentials of the two logic output terminals TH and THX become equal.
The potential at this instant is slightly larger than the threshold value of the MOS, therefore a state where the NMOS transistors NT11 and NT12 weakly become ON is exhibited. As a result, the current is slightly discharged through them. Accordingly, at the next instant, the potentials of the logic output terminals TH and THX become almost equal to the threshold value of the MOS.
A duality logic tree 20 is configured by for example NMOS transistors NT21 to NT34 is connected to the logic input terminals TF and TFX of the sense amplifier circuit 10 of the DCSL3 type having such a configuration and function as shown in FIG. 4, whereby a dynamic logic circuit is realized.
A "dynamic logic oircuit", as explained above, means a logic circuit of a type alternating between two phases, that is, an "idle phase" where it initializes the potential of the internal nodes and the "working phase" where it evaluates the logic function according to an input signal and defines the potential of the output node, according to a control signal. Generally, a clock is used for the control signal.
As explained above, in the sense amplifier circuit 10 of the DCSL3 type, in the idle phase, the internal nodes, that is, the logic outputs H and H_X, are initialized to the logic "0".
In the working phase for judging the logic, the NMOS transistors NT13 and NT14 of FIG. 1 become a conductive state and the current flows to the logic tree 20 through the PMOS transistors PT11 to PT13.
At this time, either of the logic inputs F and F_X always has a route reaching the ground, while the other is cut off on the middle of the route.
Accordingly, a difference arises in magnitude between the current flowing to the logic input terminal TF and the current flowing to the logic input terminal TFX.
In FIG. 1, the sense amplifier configured by the PMOS transistors PT11 to PT13 and the NMOS transistors NT11 and NT12 increases the potential difference between the logic outputs (nodes) H and H_X according to the difference of the currents and finally reaches and defines the logic potential.
However, the differential sense amplifier circuit 10 of the above DCSL3 type suffers from the following three problems.
A first problem of the DCSL3 type is that the completion signal DONE indicating the definition of the logic is not complete. An explanation will be made of this first problem in relation to FIG. 5.
FIG. 5 is a view of the state of the completion signal DONE when the phase switches from the idle phase to the working phase.
As apparent from FIG. 5, the completion signal DONE in the idle phase is much larger than the threshold value of the NMOS transistor and no longer means "0".
Further, the timing at which the phase becomes the working phase and the completion signal DONE rises is clearly different from the timing of definition of the logic outputs H and H_X.
Accordingly, there is an apprehension that a later logic circuit configured so as to refer to the completion signal DONE will end up malfunctioning.
A second problem of the DCSL3 type is that the potentials of the logic outputs H and H_X in the idle phase do not become completely 0V. As mentioned above, the potentials become close to the threshold value of the NMOS transistor.
Even in an MOS in which potential not more than the threshold value is added to the gate electrode and which becomes out off, a drain current actually flows. In general, this will be referred to as a leakage current (or cutoff leak). It has been known that the amount of the current changes exponentially with respect to the gate potential.
A concrete example thereof will be shown in FIGS. 6A and 6B.
FIGS. 6A and 6B are an explanatory view of the leakage current of a CMOS inverter, in which FIG. 6A is a circuit diagram of a simulation subject, and FIG. 6B is a view of the simulation results, that is, the output voltage and leakage current versus the input voltage characteristics.
Specifically, FIG. 6B collects the output voltages and the leakage currents when the potentials of the input terminals are changed from 0V to the current voltage (1.5V) with respect to the CMOS inverter as shown in FIG. 6A of the same figure.
Here, from FIG. 2 etc., the potentials of the outputs H and H_X in the idle phase are regarded to be in the vicinity of 0.2V.
According to FIG. 6B, the leakage current flowing when the input voltage is 0.2V is 100 times that when the input voltage is 0.0V.
Accordingly, in a differential sense amplifier circuit of the DCSL3 type, there is a problem that the power consumption becomes large when the clrcuit is stopped.
A third problem of the DCSL3 type is the malfunction of the sense amplifier due to coupling noise.
A parasitic capacity component exists between two interconnections which are extremely close in distance. If potential fluctuation occurs in one interconnection, a displacement current proportional to a time differentiation of the fluctuated potential difference flows to the adjacent interconnection through the parasitic capacitance and causes a potential fluctuation. Such an improper potential fluctuation is referred to as coupling noise.
FIG. 7 is a view of a model for evaluation of the resistance to coupling noise.
In an evaluation model 30, existence of parasitic capacitances C31 to C40 is assumed at the periphery of the sense amplifier circuit 10, so noise is given from noise voltage sources 31 to 35 through nodes NZ1 to NZ5 to the nodes H, H_X, F, and F_X inside the sense amplifier.
For example, if a rising signal is input to the node NZ1, the voltage of the node H slightly rises under its influence.
FIG. 8 is a view of the operation waveform when applying this model to a sense amplifier circuit 10 of the DCSL3 type and where a falling signal is given to the node NZ1 at a timing about the same as the falling of the clock inverted signal CLK_X.
The condition of the input signal at this time is the same as that in FIG. 2. In normal operation, H becomes equal to 1 and H_X becomes equal to 0.
In FIG. 8, however, H becomes equal to 0 and H_X becomes equal to 1. In the figure, a phenomenon where the potential of the logic output H is lower than the potential of the logic output H_X is seen during the period during which the node NZ1 falls.
This does not occur in FIG. 2 in which no noise is given. In FIG. 2, during the period in which the voltage of the logic output H must be equal to that of H_X in FIG. 2, the potential of the logic output H becomes lower, though only slightly, under the influence of the node NZ1 in FIG. 8.
The sense amplifier circuit 10 increases this improperly occurring potential difference and ends up defining an erroneous logic value.
The fact that the circuit will malfunction upon receipt of a falling signal from the outside at almost the same timing as when the clock inverted signal CLK_X falls suggests the possibility of an occurrence of a malfunction by the falling of the clock inverted signal CLK_X caused in an adjacent cell employing the DCSL3 type.
Such an unstable circuit is not practical.